- S.Chandra, K.Lahiri, A.Raghunathan, and S.Dey, "Variation-aware
System-level Power Analysis", IEEE Trans. VLSI Systems. (to appear).
pdf
- S.Chandra, K.Lahiri, A.Raghunathan, and S.Dey, "Variation-Tolerant
Dynamic Power
Management at the System-Level", IEEE Trans. VLSI Systems. (to appear).
pdf
- S.Chandra, K.Lahiri, A.Raghunathan, S.Dey, "System-on-chip Power
Management Considering Leakage Process Variations", in Proc. Design
Automation Conference (DAC), June 2007.
- S.Chandra, K.Lahiri, A.Raghunathan, S.Dey, "Considering Process
Variations during System Level Power Analysis", in Proc. International
Symposium on Low Power Electronics and Design (ISLPED), pp. 342-345,
October 2006.
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