Modeling and Minimization of Interconnect Energy Dissipation in Nanometer Technologies
Currently, the semiconductor industry is continuing to develop and implement smaller technology sizes, enabling a host of new and more powerful applications. However, as technology sizes continue to decrease, many new effects are being observed due to the use of nanometer technologies. Some significant deep sub-micron (DSM) effects are caused by increasing cross-coupling capacitance and inductance, the effects being most significant in global interconnects (such as buses connecting the components in a system-on-chip).
Recent studies on the effects caused by nanometer technologies focus primarily on timing and noise/signal integrity. In our work, we study energy dissipation in nanometer technology interconnects. Our results show that not only is there a significant increase in the energy consumed in DSM technology interconnects, but also the energy consumed is very dependent on the type of the signal transitions.
Current techniques for estimating the energy consumption of interconnects typically rely on the number of transitions to compute average power. However, because energy dissipation due to cross-coupling capacitances can vary depending on the type of transitions that are transmitted across the interconnects, traditional power estimation techniques do not accurately predict the energy dissipation of nanometer technology interconnects. For example, in Figure 1, the energy consumption of three different types of transitions are shown on a 5-wire bus system for varying lengths of the interconnects, where R represents a rising transition, F a falling transition, and 0 indicates no transition. If a transition-count based energy estimator is used, the bottom plot (with transition type RR0RR) would be estimated to have 4/5th the energy consumption of the top plot (RFRFR) as the bottom plot has 4 transitions and the top plot has 5. However, as shown in Figure 1, the RFRFR type of transition consumes 6.7 times the energy of the RR0RR type of transition for a 5mm interconnect. Therefore, in this work, we look at efficient methods for estimating the energy dissipation in nanometer interconnects.
Figure 1. Energy consumption of different types of transitions
in nanometer technologies
Moreover, recent methods that have been proposed to reduce energy dissipation in on-chip interconnects focus on minimizing the number of transitions on the interconnects. However, for interconnects in nanometer technologies, techniques need to be developed which take into account DSM effects, not just the number of transitions.
Since DSM effects can significantly impact the energy consumed in long interconnects, it is necessary to model the effect of nanometer technologies on interconnect energy dissipation at a high level so that designers can be aware of the energy consumption of their designs. Figure 2 shows the energy dissipation estimates of a transition-count based methodology vs our DSM-aware energy estimation for 10 different sets of bus transition vectors. Note that the transition-count based methodology can have significant errors, and varies widely depending on the type of data that is being sent across the bus, while our new methodology has significantly smaller errors from the actual value. (For a complete description of our methodology, please download and read our paper below.)
| Data Set | Transition-count based estimate | DSM-Aware estimation |
| 1 | 348% | 14% |
| 2 | 17% | 10% |
| 3 | 29% | 9% |
| 4 | 37% | 6% |
| 5 | 532% | 19% |
| 6 | 52% | 9% |
| 7 | 97% | 9% |
| 8 | 822% | 21% |
| 9 | 37% | 10% |
| 10 | 39% | 6% |
Most power minimization techniques available today do not consider the effects of nanometer technologies on power consumption but focus solely on minimizing the number of transitions on the interconnects. We propose a methodology for minimizing energy consumption considering DSM effects which can lower the energy dissipation by up to 50%, even though the number of transitions may increase.
To minimize the energy consumption due to DSM effects, we propose the insertion of non-data lines, allowing for a tradeoff between area overhead and energy savings. Figure 3 presents the result of inserting an increasing number of non-data lines on the energy savings obtained. The data sets include JPEG image compression bus traces, software benchmark address traces, and random data transitions on the bus. Figure 3 shows that as the constraint on the number of non-data lines allowed increases (x axes), the energy savings also increase (y axes). As shown in Figure 3, energy savings of up to 50% are possible using the insertion of non-data lines. In addition, for some types of data (e.g. address), fewer non-data lines can be inserted leading to lower area overhead while still obtaining significant energy savings.
Figure 3. Energy savings obtained through insertion of non-data
lines