Adaptive System-on-chip Architectures for Mobile Multimedia Communication


Principal Investigator: Sujit Dey, PhD
Graduate Students: Clark N. Taylor, Debashis Panigrahi, Dong-Gi Lee

Project Summary

Motivation

With the recent advent of wireless (mobile) communications and the internet, there is a growing demand to allow for high-throughput, low-power communications. In addition to voice and data communications, the need for image and video communication over wireless channels is quickly increasing. One way to design an architecture supporting mobile multimedia is to assume the worst-case conditions and requirements. However, significant reductions in bandwidth and energy consumption are available through adapting to current communication and application conditions and requirements. (For more information on adapting to current conditions and requirements, please see our mobile multimedia algorithms page.) To enable adaptation to current conditions and requirements to lower the consumption of energy and bandwidth, we are designing an adaptive system-on-chip architecture.

Approach

In Figure 1, we present a functional overview of our proposed mobile multimedia architecture. Our new architecture includes some components of a traditional wireless appliance (teal), such as a voice/data coder, channel coder, RF modulator, and power amplifier. It also includes two new components that we are developing for adaptive multimedia communication: the adaptive image/video coder and run-time adaptation algorithms. The run-time reconfiguration system is responsible for understanding the current network conditions and service requirements, and configuring the other architecture components accordingly.


Figure 1. Functional View of Adaptive Mobile Multimedia Communication Architecture

To effectively implement an architecture that enables mobile multimedia communication, several requirements must be met. First, the architecture should be as low-power and efficient as possible to help overcome the energy bottleneck to multimedia communication. Second, the architecture must be able to meet the real-time requirements of multimedia communication. Third, the architecture should be flexible enough to enable adaptation to current communication conditions and requirements, allowing further savings of energy and bandwidth, overcoming the bandwidth and energy limitations of mobile multimedia communication.

Current Work

We have developed and implemented at the RTL level an adaptive image compression system-on-chip shown in Figure 2. Our hardware/software system includes a general-purpose picoJava processor core, hardware accelerators (DCT and DWT), on-chip memories, and the PI-BUS on-chip system bus. To enable mobile multimedia communication, our architecture had to be flexible enough to run different image compression algorithms, with differing parameters, while still achieving extremely energy and time-efficient performance. We achieved these seemingly contradictory goals through judicious hardware/software mapping of image compression algorithm tasks.


Figure 2. Adaptive Image Compression System-on-Chip Architecture

Traditional hardware/software co-design methodologies try to perform the mapping of algorithm tasks solely on the basis of performance and power requirements. However, for mobile multimedia communication, we also needed to consider adaptability as an objective in mapping the tasks to a hardware/software architecture. It is well known that any software component of a system is easily configurable whereas hardware components offer less dynamic configurability. However, implementing a task in hardware results in better performance and reduced energy consumption.

Image compression algorithms generally consist of three major tasks: (1) image transformation, (2) quantization, and (3) encoding. Even though image compression algorithms may differ greatly in their encoding and quantization steps, they often have an identical transform step. In addition, the transform step is usually the most compute-intensive portion of image compression algorithms. Therefore, by mapping the transforms (DCT and DWT) to hardware accelerators, great energy and performance efficiency gains can be made, while maintaining the flexibility needed to reduce energy and bandwidth consumption for mobile multimedia communication. Similarly, quantization operations can be performed in hardware without a reduction in flexibility. However, to allow for implementation of several different image compression algortihms, the encoding step is performed in software.

By performing judicious hardware/software mapping, with an a-priori knowledge of the characteristics of image compression algorithms, we have designed an architecture which enables adaptive, high-performance, low-energy image compression.

In the future, we will apply our hardware/software mapping techniques described here to turbo coding (a channel coding algorithm) and video codecs top enable adaptive and high-performance wireless multimedia communication.

Papers

C. N. Taylor, D. Panigrahi, S. Dey, "Design of an Adaptive Architecture for Energy Efficient Wireless Image Communication", accepted for publication in Lecture Notes in Computer Science, Springer Verlag.

D. Panigrahi, C.N. Taylor, S. Dey, "A Hardware/Software Reconfigurable Architecture for Adaptive Wireless Image Communication", accepted for publication in Proc. 2002 VLSI Design Conference/ASP-DAC.

Presentations

Present ation at the CWC Annual Research Review, San Diego, California, May 2000.
For any comments or questions, please contact Clark Taylor

Last modified on 12 Dec 2001.