Mobile Embedded Systems Design and Test
Dept of Electrical
and Computer Engineering
University of California,
San Diego
Publications are grouped into
the following areas:
- Adaptive Wireless Applications
and Protocols
- Configurable
HW/SW Embedded System Design
- Low Power
Embedded Nanochips
- Validation
and Test of Nanometer SoCs
- Low Cost
Reliable Data Aggregation for Wireless Sensor Networks
Adaptive
Wireless Applications and Protocols
- S.Mukhopadhyay, C.Schurgers, S.Dey,
"Joint Computation and Communication Scheduling to Enable Rich Mobile Applications,"
to appear in IEEE Global Communications Conference (Globecom'07), Washington D.C., November, 2007.
- N.Ramos, S.Dey, "A Device and Network-Aware Scaling
Framework for Efficient Delivery of Scalable Video over Wireless
Networks," in IEEE International Symposium on Personal, Indoor
and Mobile Radio Communications, September 2007.
pdf
- S.Chandra, S.Dey, "Addressing Computational and Networking
Constraints to Enable Video Streaming from Wireless Appliances", in
Proc. of Workshop on Embedded Systems for Real- Time Multimedia
(ESTIMEDIA), September 2005.
- N.Ramos, D.Panigrahi, S.Dey, "Dynamic Adaptation Policies to
Improve Quality of Service of Real-Time Multimedia Applications in IEEE
802.11e WLAN Networks", in Springer Wireless Networks,
Vol. 13, No. 4, Aug. 2007, pp. 511-535.
link
- N.Ramos, D.Panigrahi, S.Dey, "Quality of Service Provisioning in 802.11e
Networks: Challenges, Approaches, and Future Directions," in IEEE Networks
Magazine, Vol. 19, No. 4, pp.14-20, July/Aug 2005. pdf
- Dong-Gi Lee and Sujit Dey, "Dynamic End-to-End Image Adaptation for
Guaranteed Quality of Service in Wireless Image Data Services", in
Proceedings
of IEEE Wireless Communications and Networking Conference (WCNC 2005),
March
2005.
- N.Ramos, D.Panigrahi, S.Dey, "Dynamic Adaptation Policies to
Improve Quality of Service of Multimedia Applications in WLAN Networks",
in ICST/IEEE Intl. Workshop on Broadband Wireless Multimedia,
San Jose, CA, October 2004. pdf
- Dong-Gi Lee and Sujit Dey, "SIQuA: Server-aware Image Quality
Adaptation
for Optimizing Server Latency and Capacity in Wireless Image Data
Services",
in Proceedings of IEEE Vehicular Technology Conference 2004 - Fall (VTC
2004 -
Fall), September 2004. pdf
- Dong-Gi Lee and Sujit Dey, "Dynamic image adaptation technique and
architecture to enhance server performance in wireless image services",
in
Proceedings of IEEE International Symposium on Personal, Indoor and
Mobile
Radio Communications (PIMRC), September 2004. pdf
- Dong-Gi Lee and Sujit Dey, "Addressing Server Latency and Capacity
to Enable Fast and Affordable Wireless Image Data Services," in 1st Workshop
on Embedded Systems for Real-time Multimedia, pp.40-47, Newport Beach, October
2003. pdf
- N.Ramos, D.Panigrahi, S.Dey, "ChaPLeT: Channel-dependent Packet Level
Tuning for Service Differentiation in IEEE 802.11e," in International Symposium
on Wireless Personal Multimedia Communications, pp.86-90, Yokosuka,
Kanagawa,
Japan, October 2003. pdf
- N.Ramos, D.Panigrahi, S.Dey, "Energy-Efficient Link Adaptations
in IEEE 802.11b Wireless LAN", in IASTED Intl. Conf. on Wireless and Optical
Communications, pp. 578-583, Banff, Alberta, July 2003. pdf
- D.G.Lee, D.Panigrahi, S.Dey, "Network-Aware Image Data Shaping for
Low-Latency and Energy-Efficient Data Services over the Palm Wireless Network",
in World Wireless Congress (3G Wireless), San Francisco, May 2003. pdf
- Young-Ho Seo, Dong-Wook Kim, Ji-Sang Yoo, Sujit Dey, and Abhishek
Agrawal, "Wavelet Domain Image Encryption by Subband Selection and Data
Bit Selection", in World Wide Congress (3G Wireless), San Francisco, May
2003. pdf
- D. Panigrahi, F. Khaleghi, "Enabling Trade-offs between System Throughput
and Fairness in Wireless Data Scheduling Techniques," in World Wide Congress
(3G Wireless), San Francisco, May 2003. pdf
- D.Panigrahi, S.Dey, A.Raghunathan, "Network Aware Content Shaping
for Energy Efficient Wireless Web Access", Chapter in book, System-Level
Power Optimization For Wireless Multimedia Communications, Ch.10, Kluwer
Academic Publishers, 2002.
- D.G.Lee, S.Dey, "Adaptive and Energy Efficient Wavelet Image
Compression For Mobile Multimedia Data Services", in Proc. Intl. Conf. on
Communications, vol.4, pp. 2484-2490, New York, April 2002. pdf
- C.N.Taylor, S.Dey, "Adaptive Image Compression for Enabling
Mobile Multimedia Communication", in Proc. Intl. Conf. on Communications,
pp.1925-1929, vol.6, Helsinki, June 2001. pdf
- D.Panigrahi, A.Raghunathan, G.Lakshminarayana, S.Dey, "Energy
Modeling for Wireless Internet Access", in Proc. Intl. Conf. on Third Generation
Wireless and Beyond, pp.332-337, San Francisco, May 2001. pdf
- C.N.Taylor, S.Dey, D.Panigrahi, "Energy/Latency/Image Quality
Tradeoffs in Enabling Mobile Multimedia Communications", in Proc. Software
Radio: Technologies and Services, Enrico Del Re, Springer Verlag Ltd., pp.
55-66, Springer Verlag, January 2001. pdf
Back to top
Configurable HW/SW Embedded Systems
-
K.Sekar, K.Lahiri, A.Raghunathan, S.Dey "Integrated Data Relocation and
Bus Reconfiguration for Adaptive SoC Platforms", Proc. Design Automation
and Test in Europe (DATE), Munich, March 2006.
-
K.Sekar, K.Lahiri, A.Raghunathan, S.Dey, "FLEXBUS: A High Performance
System-on-Chip Communication Architecture with a Dynamically Configurable
Topology", in Proc. Design Automation Conf., pp. 571-574, Anaheim, June
2005. pdf
-
K.Lahiri, S.Dey, A.Raghunathan, "Design of Communication Architectures
for High-Performance and Energy-Efficient System-on-Chips", book
chapter, in Multiprocessor Systems-on-Chips , Morgan Kaufmann, September
2004.
-
K.Lahiri, A.Raghunathan, S.Dey, "Efficient Power Profiling for
Battery-Driven Embedded System Design", IEEE Trans. on Computer-Aided
Design of Integrated Circuits and Systems , vol.23, no.6, June 2004.
pdf
- K.Lahiri, A.Raghunathan, S.Dey, "Design
of High-Performance
System-on-Chips using Communication Architecture Tuners", IEEE Trans.
on Computer-Aided Design of Integrated Circuits and Systems, vol.23,
no.5, pp. 620-636, May 2004. pdf
- K.Sekar, K.Lahiri, S.Dey, "Configurable
Platforms With Dynamic Platform Management: An Efficient Alternative to
Application-Specific System-on-Chips", Proc. International Conference on
VLSI Design, Mumbai, India, Jan 2004. pdf
- K.Sekar, K.Lahiri, S.Dey, "Dynamic Platform Management for Configurable
Platform-Based System-on-Chips", Proc. International Conference on Computer-Aided
Design, pp. 641-648, San Jose, Nov 2003. pdf
- K.Lahiri, A.Raghunathan, S.Dey, "Design Space Exploration for
Optimizing On-Chip Communication Architectures", IEEE Trans. on
Computer-Aided
Design of Integrated Circuits and Systems, vol.23, no.6, June 2004.
pdf
- K.Lahiri, A.Raghunathan, S.Dey, "Communication Based Power Management",
IEEE Design and Test of Computers, vol.19, no.4, pp.118-130, July-August
2002 (appears in Special DAC Section). pdf
- K.Lahiri, A.Raghunathan, S.Dey, "Communication Architecture Based
Power Management for Battery-Efficient System Design", in Proc. Design
Automation Conf., pp.691-696, New Orleans, June 2002 (Among 5 papers
chosen as the Best of DAC in Practice). pdf
- K.Lahiri, A.Raghunathan, S.Dey, "Fast System-Level Power Profiling
for Battery-Efficient System Design", in Proc. Intl. Symp. on HW/SW Co-design,
pp.157-162, Estes Park, May 2002. pdf
- K.Lahiri, A.Raghunathan, S.Dey, "Battery-Efficient Architecture
for an 802.11 MAC Processor", in Proc. Intl. Conf. on Communications, vol.2,
pp.669-677, New York, April 2002. pdf
- C.N.Taylor, D.Panigrahi, S.Dey, "Design of an Adaptive Architecture
for Energy Efficient Wireless Image Communication", Lecture Notes in Computer
Science, vol.2268, pp.260-273, Springer-Verlag, 2002. pdf
- D.Panigrahi, C.N.Taylor, S.Dey, "A Hardware/Software Reconfigurable
Architecture for Adaptive Wireless Image Communication", in Proc. Intl. Conf.
on VLSI Design/ASP-DAC, pp.553-558, Bangalore, January 2002. pdf
- K.Lahiri, A.Raghunathan, G.Lakshminarayana, "LOTTERYBUS:
A New High-Performance Communication Architecture for System-on-Chip Designs",
in Proc. Design Automation Conf, pp.15-20, Las Vegas, June 2001. pdf
- K.Lahiri, A.Raghunathan, S.Dey, "System-Level Performance
Analysis for Designing On-Chip Communication Architectures", IEEE Trans.
on Computer-Aided Design of Integrated Circuits and Systems, vol. 20,
no.6, pp.768-783, June 2001. pdf
- D.Panigrahi, C.Chiasserini, S.Dey, R.Rao, A.Raghunathan, K.Lahiri,
"Battery Life Estimation for Mobile Embedded Systems", in Proc. Intl. Conf.
on VLSI Design, pp.57-63, Bangalore, January 2001. pdf
- K.Lahiri, A.Raghunathan, S.Dey, "Evaluation of the Traffic-Performance
Characteristics of System-on-Chip Communication Architectures", in Proc.
Intl. Conf. on VLSI Design, pp.21-35, Bangalore, January 2001. pdf
- K.Lahiri, A.Raghunathan, S.Dey, "Efficient Exploration of the SoC
Communication Architecture Design Space", in Proc. Intl. Conf. on Computer-Aided
Design, pp.424-430, San Jose, November 2000. pdf
- K.Lahiri, G.Lakshminarayana, A.Raghunathan, S.Dey, "Communication
Architecture Tuners: A Methodology for the Design of High-Performance Communication
Architectures for System-on-Chips", in Proc. Design Automation Conf., pp.513-518,
Los Angeles, June 2000 (Best Paper Award). pdf
- M.Lajolo, A.Raghunathan, S.Dey, L.Lavagno, "Efficient Power
Co-Estimation Techniques for Systems-on-Chip Design", in Proc. Design Automation
and Test in Europe, Paris, March 2000. pdf
- K.Lahiri, A.Raghunathan, S.Dey, "Performance Analysis of Systems
with Multi-Channel Communication Architectures", in Proc. Intl. Conf. on
VLSI Design, pp.530-537, Calcutta, January 2000. pdf
- K.Lahiri, A.Raghunathan, S.Dey,"Fast Performance Analysis of Bus-based
System-on-Chip Communication Architectures", in Proc. Intl. Conf. on Computer-Aided
Design, pp.566-572, San Jose, November 1999. pdf
Back to top
Low Power Wireless
Embedded Nanochips
- S.Chandra, K.Lahiri, A.Raghunathan, S.Dey, "System-on-chip Power
Management Considering Leakage Process Variations", in Proc. Design
Automation Conference (DAC), June 2007.
- S.Chandra, K.Lahiri, A.Raghunathan, S.Dey, "Considering Process
Variations during System Level Power Analysis", in Proc. International
Symposium on Low Power Electronics and Design (ISLPED), pp. 342-345,
October 2006.
- A.Raghunathan, S.Dey, N.K.Jha, "High-Level
Macro-Modeling and Estimation Techniques for Switching Activity and Power
Consumption", to appear, IEEE Trans. on VLSI Systems. coming soon
- G.Lakshminarayana, A.Raghunathan, K.S.Khouri, N.K.Jha, S.Dey, "Common
Case Computation: A New Paradigm for Energy and Performance Optimization",
to appear in IEEE Trans. on Computer-Aided Design of Integrated Circuits
and Systems. coming soon
- K.Lahiri, A.Raghunathan, S.Dey, "Communication Based Power Management",
IEEE Design and Test of Computers, vol.19, no.4, pp.118-130, July-August
2002. (appears in Special DAC Section). pdf
- K.Lahiri, A.Raghunathan, S.Dey, "Communication Architecture Based
Power Management for Battery-Efficient System Design", in Proc. Design Automation
Conf., pp.691-696, New Orleans, June 2002 (Among 5 papers chosen as
the Best of DAC in Practice). pdf
- K.Lahiri, A.Raghunathan, S.Dey, "Fast System-Level Power Profiling
for Battery-Efficient System Design", in Proc. Intl. Symp. HW/SW Co-design,
pp.157-162, Estes Park, May 2002. pdf
- K.Lahiri, A.Raghunathan, S.Dey, "Battery-Efficient Architecture
for an 802.11 MAC Processor", in Proc. Intl. Conf. on Communications, vol.2,
pp.669-677, New York, April 2002. pdf
- C.N.Taylor, D.Panigrahi, S.Dey, "Design of an Adaptive Architecture
for Energy Efficient Wireless Image Communication", Lecture Notes in Computer
Science, vol.2268, pp.260-273, Springer-Verlag, 2002. pdf
- K.Lahiri, A.Raghunathan, S.Dey, D.Panigrahi, "Battery-Driven
System Design: A New Frontier in Low Power Design", in Proc. Intl. Conf.
on VLSI Design/ASP-DAC, pp.261-267, Bangalore, January 2002. pdf
- C.N.Taylor, S.Dey, Y.Zhao, "Modeling and Minimization of Interconnect
Energy Dissipation in Nanometer Technologies", in Proc. Design Automation
Conf., pp. 754-757, June 2001. pdf
- D.Panigrahi, A.Raghunathan, G.Lakhsminarayana, S.Dey, "Energy
Modeling for Wireless Internet Access", in Proc. Intl. Conf. on Third Generation
Wireless and Beyond, San Francisco, pp.332-337, May 2001. pdf
- D.Panigrahi, C.Chiasserini, S.Dey, R.Rao, A.Raghunathan,
K.Lahiri, "Battery Life Estimation for Mobile Embedded Systems", in Proc.
Intl. Conf. on VLSI Design, pp.55-63, Bangalore, January 2001. pdf
- M.Lajolo, A.Raghunathan, S.Dey, L.Lavagno, "Efficient Power
Co-Estimation Techniques for System-on-Chip Designs", in Proc. Design Automation
and Test in Europe, March 2000.
- G.Lakshminarayana, A.Raghunathan, K.S.Khouri, N.K.Jha, S.Dey, "Common-case
computation: A high-level power optimization technique", in Proc. Design
Automation Conf., June 1999.(Best Paper Award)
- M.Lajolo, A.Raghunathan, S.Dey, L.Lavagno, A. Sangiovanni-Vincentelli,
"Efficient Power Estimation Techniques for HW/SW Systems," in Proc. IEEE
VOLTA, March 1999.
- G.Lakshminarayana, A.Raghunathan, N.K.Jha, S.Dey, "Power Management
in High Level Synthesis", IEEE Trans. on VLSI Systems, March 1999.
- G.Lakshminarayana, A.Raghunathan, N.K.Jha, S.Dey, "Transforming control-flow
intensive designs to facilitate power management", in Proc. Intl. Conf. on
Computer-Aided Design, November 1998.
- G.Lakshminarayana, A.Raghunathan, N.K.Jha, S.Dey, "A Power Management
Methodology for High-Level Synthesis," in Proc. Intl. Conf. on VLSI Design,
January 1998 (Best Paper Award).
- A.Raghunathan, S.Dey, N.K.Jha, K.Wakabayashi, "Power Management Techniques
for Control-Flow Intensive Designs," in Proc. Design Automation Conf., June
1997.
- A.Raghunathan, S.Dey, N.K.Jha, "Register-Transfer-Level Power Estimation
Techniques for Control-Flow Intensive Designs," in Proc. Design Automation
Conf., June 1997.
- A.Raghunathan, N.K.Jha, S.Dey, "High Level Power Analysis and Optimization",
Kluwer Academic Publishers, Boston, MA, November 1997.
- A.Raghunathan, S.Dey, N.K.Jha, "Register-Transfer Level Estimation
Techniques for Switching Activity and Power Consumption," in Proc. Intl.
Conf. on Computer-Aided Design, November 1996.
- A.Raghunathan, S.Dey, N.K.Jha, K.Wakabayashi, "Controller Re-specification
to Minimize Switching Activity in Controller/Data Path Circuits," in Proc.
Intl. Symp. on Low Power Electronics and Design, August 1996.
- A.Raghunathan, S.Dey, N.K.Jha, "Glitch Analysis and Reduction in
Register Transfer Level Power Optimization," in Proc. Design Automation
Conf., June 1996.
- M.Potkonjak, P.Ashar, S.Dey, T.Misawa, R.K.Roy, "Synthesis techniques
for low power digital systems," NEC Research and Development Journal, vol.36,
No.1, pp.83-102, January, 1995.
Back to top
Validation and Test
of Nanometer Technology SoCs
- Chong Zhao, Xiaoliang Bai, Sujit Dey, "Efficient transient error effects in digital nanometer circuits,"
to appear in IEEE Transactions on Reliability.
- Chong Zhao, Yi Zhao, Sujit Dey, "An Intelligent Robustness Insertion Methodology for Optimal Transient Error
Tolerance", to appear in IEEE transaction on Very Large Scale Integration Systems.
- Chong Zhao, Sujit Dey, "Modeling Soft Error Effects Considering Process Variations," to appear in
International Conference on Computer Deisgn (ICCD), October 2007, Lake Tahoe, California.
- Chong Zhao, Sujit Dey, "Evaluating and Improving Transient Error Tolerance of CMOS Digital VLSI Circuits," in
Proceedings of the International Test Conference 2006 (ITC), pp.29.1, October 2006, Santa Clara, California.
- Chong Zhao, Sujit Dey, "Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO)", in Proceedings of 7th International Symposium on Quality Electronic Design (ISQED), pp. 133-138, March 2006, San Jose, California, USA. paper and talk. Best Paper Award
- Chong Zhao, Xiaoliang Bai, Sujit Dey, "A Static Noise Impact Analysis Methodology for Evaluating Transient Error Effects in Digital VLSI Circuits", in Proceedings of International Test Conference 2005, pp. 40.2, October, 2005, Austin, Texas, USA. paper and talk
- Chong Zhao, Yi Zhao, Sujit Dey, "Constraint-Aware Robustness Insertion for Optimal Noise-Tolerance Enhancement in VLSI Circuits," in Proceedings of 42nd Design Automation Conference, pp. 190-195, June 2005, Anaheim, California, USA. paper and talk
- Chong Zhao, Xiaoliang Bai, Sujit Dey, "Soft Spot Analysis: A Scalable Methodology Targeting Compound Noise Effects in Nano-meter Circuits", IEEE Design & Test of Computers, Volume 22, Issue 4, July-Aug. 2005, pp. 362-375. pdf
- Xiaoliang Bai, Sujit Dey, "High-level Crosstalk Defect Simulation Methodology for System-on-Chip Interconnects," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol 23, NO. 9, September 2004. pp. 1355~1361. pdf
- Xiaoliang Bai, Rajit Chandra, Sujit Dey and P. V. Srinivas, "Interconnect Coupling-Aware Driver Modeling in Static Noise Analysis for Nanometer Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, NO. 8, August 2004. pp. 1256~1263. pdf
- Chong Zhao, Xiaoliang Bai, Sujit Dey, "A Scalable Soft Spot Analysis Methodology for Compount Noise Effects in Nano-meter Circuits", DAC'04, San Diego, California, June 7-11, 2004. pdf
- X. Bai, L. Chen and S. Dey, "Software-Based
Self-Test Methodology for Crosstalk Faults in Processors," in IEEE International
High Level Design Validation and Test Workshop, pp.11-16, San Francisco,
November 2003. pdf
- Y. Zhao, L. Chen, S. Dey, "On-line testing of multi-source noise-induced
errors on the interconnects and buses of system-on-chips," in Global Semiconductors,
Vol. 4, pp.94-97, May 2003. pdf
- X.Bai, S.Dey, A.Krstic, "ATPG for Crosstalk using Hybrid Structural
SAT," in Intl. Test Conference, pp.112-121, Charlotter, Oct. 2003. pdf
- Y.Zhao, S.Dey, "Fault Coverage Analysis Techniques of Crosstalk
in Chip Interconnects," in IEEE Trans. on Computer-Aided Design of Integrated
Circuits and Systems, vol. 22, No. 6, pp.770-782, June 2003. pdf
- Y.Zhao, S.Dey, "Separate Dual Transistor Registor-an Circuit Solution
for on-line Testing of Transient Errors in UDSM-IC," in Proc. Intl. On-line
Testing Symposium 2003, pp.7-11, Kos Island, Greece, June 2003. pdf
- L.Chen, S.Ravi, A.Raghunathan, S.Dey, "A Scalable Software-Based
Self-Test Methodology for Programmable Processors," in Proc.Design Automation
Conf., pp. 548-553, Anaheim, CA, June 2003 (Best Paper Award Candidate).
pdf
- K.Sekar, S.Dey, "LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic
Cores and Interconnects," Journal of Electronic Testing: Theory and
Applications, vol.19, no.2, pp.113-123, April 2003. pdf
- X.Bai, R.Chandra, S.Dey, P.V.Srinivas, "Noise-Aware Driver Modeling",
Proc. of the Intl. Symp.on Quality Electronic Design, pp.177-182, San Jose,
March 2003. pdf
- Y.Zhao, L.Chen, S.Dey, "On-line Testing for Multi-source Noise-induced
Errors in System-on-Chip Interconnects and Buses," in Proc. Intl. Test
Conference, pp.491-499, Baltimore, October 2002. pdf
- A.Krstic, L.Chen, W.-C.Lai, K.-T.Cheng, S.Dey, "Embedded Software-Based
Self-Test for Programmable Core-Based Designs," IEEE Design and Test of
Computers, vol.19, no.4, July 2002, pp.18-27. pdf
- L.Chen, X.Bai, S.Dey, "Testing for interconnect crosstalk
defects using on-chip embedded processor cores," Journal of Electronic
Testing: Theory and Applications, vol.18, no.4, August 2002, pp. 529-538.
pdf
- L.Chen, S.Dey, "Software-Based Diagnosis for Processors," in Proc.
Design Automation Conf., pp.259-262, New Orleans, June 2002. pdf
- A.Krstic, L.Chen, W.-C.Lai, K.-T.Cheng, S.Dey, "Embedded Software-Based
Self-Testing for SoC Design," in Proc. Design Automation Conf., New Orleans,
June 2002, pp.355-360. pdf
- K.Sekar, S.Dey, "LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic
Cores and Interconnects," in Proc. VLSI Test Symposium, Monterey, May 2002.
pdf
- I.Ghosh, K.Sekar, V.Boppana, "Design for Verification at
the Register Transfer Level", in Intl. Conf. on VLSI Design/ASP-DAC, pp.420-425,
Bangalore, January 2002. pdf
- L.Chen, X.Bai, S.Dey, "Testing for interconnect crosstalk defects
using on-chip embedded processor cores," in Proc. Design Automation Conf.,
Las Vegas, June 2001. pdf
- X.Bai, S.Dey, "High-level Crosstalk Defect Simulation for
System-on-Chip Interconnects", in Proc. VLSI Test Symposium, Los Angeles,
April 2001. pp. 169-175 pdf
- P.Dasgupta, P.P.Chakrabarti, A.Nandi, K.Sekar, A.Chakrabarti,
"Abstraction of Word-level Linear Arithmetic Functions from Bit-level Component
Descriptions," in Design, Automation, and Test in Europe, pp.4-8, Munich,
March 2001. pdf
- L.Chen, S.Dey, "Software-Based Self-Testing Methodology for Processor
Cores," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems,
vol.20, no.3, pp.369-380, March 2001. pdf
- Y.Zhao, S.Dey, "Analysis of Interconnect Crosstalk Defect
Coverage of Test", in Proc. Intl. Test Conference, Atlantic City, October
2000. pdf
- D.Panigrahi, C.Taylor, S.Dey, "Interface Based Hardware/Software
Validation of a System-on-Chip,", in Proc. High-Level Design Validation
and Test Workshop (HLDVT), pp.53-58, November 2000. pdf
- S.Dey, P.Sanchez, D.Panigrahi, L.Chen, C.Taylor, K.Sekar, "Using
a Soft Core in a SOC Design: Experiences with PicoJava,", IEEE Design
and Test of Computers, vol.17, no.3, pp.60-71, July-September 2000.
pdf
- L.Chen, S.Dey, P.Sanchez, K.Sekar, Y.H.Chen, "Embedded Hardware
and Software Self-Testing Methodologies for Processor Cores," in Proc.
Design Automation Conf., Los Angeles, June 2000. pdf
- X.Bai, S.Dey, J.Rajski, "Self-Test Methodology for At-Speed
Test of Crosstalk in Chip Interconnects", in Proc. Design Automation Conf.,
Los Angeles, June 2000. pp. 619-24 pdf
- K-T.Cheng, S.Dey, M.Rodgers, K.Roy, "Test Challenges for Deep
Sub-Micron Technologies", in Proc. Design Automation Conf., Los Angeles,
June 2000.
- L.Chen, S.Dey, "DEFUSE: A Deterministic Functional Self-Test
Methodology for Processors," in Proc. VLSI Test Symposium, Montreal, April
2000. pdf
- L.Chen, S.Dey, "A Deterministic Functional Self-Test Methodology
for Processors," in Proc. Intl. High-Level Design Validation and Test Workshop,
San Diego, November 1999. pdf
- M.Cuviello, S.Dey, X.Bai, Y.Zhao, "Fault Modeling and Simulation
for Crosstalk in System-on-Chip Interconnects", in Proc. Intl. Conf. on Computer-Aided
Design, San Jose, November 1999. pp.297-303. pdf
Back to top
Low Cost Reliable Data Aggregation in Wireless Sensor Networks
- S.Mukhopadhyay, D.Panigrahi, S.Dey, "Data aware, Low cost Error correction for Wireless Sensor Networks,"
in IEEE Wireless Communications and Networking Conference, pp. 2492-7, Atlanta, March
2004. pdf
- S.Mukhopadhyay, D.Panigrahi, S.Dey, "Model Based Error Correction for Wireless Sensor Networks,"
to appear in The First IEEE Communications Society Conference on Sensor and Ad Hoc Communications and
Networks (SECON '04), pp. 575-584, Santa Clara, October 2004.
pdf
Back to top
Please address comments and
questions to naomir@ece.ucsd.edu