Glitch Analysis and Reduction in Register Transfer Level Power Optimization
A.Raghunathan, S.Dey, N.K.Jha, "Glitch Analysis and Reduction in Register Transfer Level Power Optimization," in Proc. Design Automation Conf., June 1996.
A.Raghunathan, S.Dey, N.K.Jha, "Glitch Analysis and Reduction in Register Transfer Level Power Optimization," in Proc. Design Automation Conf., June 1996.