Design for Verification at the Register Transfer Level
I.Ghosh, K.Sekar, V.Boppana, "Design for Verification at the Register Transfer Level", in Intl. Conf. on VLSI Design/ASP-DAC, pp.420-425, Bangalore, January 2002.
I.Ghosh, K.Sekar, V.Boppana, "Design for Verification at the Register Transfer Level", in Intl. Conf. on VLSI Design/ASP-DAC, pp.420-425, Bangalore, January 2002.